In handling a semiconductor chip package, electrostatic discharge (ESD) may result in damage to the semiconductor devices on the chip. On-chip protection circuits are used to provide a safe discharge path. The protection circuit is basically a switch which is off during normal circuit operation and turns on during an ESD event when a high voltage is present at a pin of the chip. Various devices can be used to accomplish this switching function. In a CMOS technology the semiconductor controlled rectifier (SCR) is ideal for this application because in its conducting state the heat generation is distributed uniformly within a large volume. One such SCR structure, referred to as the lateral SCR (LSCR) has been described in detail by Rountree, et al, in an article entitled "A Process Tolerant Input Protection Circuit for Advanced CMOS Processes" (EOS/ESD Symposium Proceedings, PP. 201-205, 1988). A typical CMOS technology in which this SCR device has been fabricated is described in "An 0.8 Micron CMOS Technology for High Performance Logic Applications," R. A. Chapman, et al., IEDM Technical Digest, 1987, PP 362-365. Both of these articles are hereby incorporated by reference.
The trigger voltage of an LSCR is generally not low enough to permit its use as the sole device for ESD protection. For the case of providing input protection for a circuit, a secondary circuit is employed in conjunction with the LSCR. This secondary circuit generally has a low clamping voltage to provide initial protection for gate oxides of the device for which input protection is sought. For example, the secondary circuit may comprise a resistor connected in series between an input pad and input of the device for which ESD protection is sought. The LSCR is then connected to and between the input pad and circuit ground. The resistor allows the voltage across the LSCR to increase to the LSCR trigger voltage at which time the current is shunted through the LSCR. For outputs, the scheme described above cannot be used because circuit performance requirements generally prohibit the use of a series resistance. Therefore, the LSCR is not useful to protect the output.
FIG. 1a illustrates a cross-sectional view of a typical LSCR. As shown, region p.sub.1 +, formed of heavily doped p-type semiconductor material, is the anode and region n.sub.2 +, formed of heavily doped n-type semiconductor material, is the cathode of the LSCR. The two base regions of the LSCR are well region n.sub.1 formed of n-type semiconductor material and region p.sub.2 formed of p-type semiconductor material such that region n.sub.1 is interposed between regions p.sub.1 + and p.sub.2 while region p.sub.2 is interposed between region n.sub.2 + and n.sub.1. Junctions are shown as j.sub.1, the boundary between regions p.sub.1 + and n.sub.1 ; j.sub.2, the boundary between regions n.sub.1 and p.sub.2 ; and j.sub.3, the boundary between regions p.sub.2 and n.sub.2 +. Regions n.sub.1 and p2 may optionally be contacted by heavily doped semiconductor material of the same type as shown by regions n+ (heavily doped n-type) and 14 (heavily doped p-type). Alternately, one or both of the base regions may be contacted from below by heavily doped regions. At a surface, the usual isolation material, such as thick oxide 6, is interposed between the anode p.sub.1+ and the cathode n.sub.2+. This LSCR device acts as a switch when the anode potential is raised positive with respect to the cathode potential. As the anode potential is raised positively, junction j2 becomes reverse biased and junctions j1 and j3 become slightly forward biased to accommodate leakage current from junction j2. Since the only current flowing is the leakage current from junction j2, the LSCR is considered to be off (known as the forward blocking state). As the anode potential is raised further, the junction j2 enters avalanche breakdown and a large number of electron-hole pairs are generated therein. The electrons enter base region n.sub.1 and the holes enter region p.sub.2 causing both junctions j1 and j3 to become more forward biased. The forward biased junctions inject additional carriers into the base regions. More specifically, electrons are injected by the cathode and holes by the anode. This results in positive feedback. This positive feedback loop is usually represented by the circuit schematic of FIG. 1b. As shown, the LSCR may be represented by npn bipolar transistor 26 and pnp bipolar transistor 28 in a constructive feedback configuration. Resistors 21 and 22 represent the resistance of each of the LSCR base regions. The chip input is labeled PAD. Regions p.sub.1+, p.sub.2, n.sub.2+ and n.sub.1 are also identified. At a certain level of feedback, instability is reached. As a result, the potential difference between the anode and the cathode collapses and the current through the device increases. In other words, the LSCR device has triggered from the off condition to the on condition (known as the forward conducting state). Once the LSCR is on, it is very robust and can shunt large currents without failing. As an example, an LSCR fabricated in the CMOS technology referenced above with a width of 100 microns can withstand a Human Body Model (HBM) ESD event in excess of 8000 V. It is important that the voltage at which the LSCR triggers is at least the breakdown voltage of junction j2. In the CMOS technology referenced above, this trigger voltage is approximately 50 Volts.
Previous SCR structures used for ESD protection can withstand high levels of ESD stress. Once the SCR is triggered, it provides very good on-chip protection. However, the problem with prior art SCR devices is their high trigger voltage. There are a variety of structures, for which ESD protection is desired, which may be damaged at voltages less than the trigger voltage of these SCRs. Therefore, an SCR alone is ineffective in providing protection for these structures. Prior art schemes of ESD protection at the input pads of a device have included an SCR as part of an input protection circuit. Unfortunately, designing such a circuit is expensive and complicated. Moreover, for output or input/output (I/O) pads, no such circuit is available. Therefore, until now, SCRs have not been useful for protecting output or I/O pads.